1. Field of the Invention
The present invention relates to an information processing device that accesses a memory, processor, and memory management method.
2. Description of the Related Art
In the conventional information processing device, a volatile memory such as a dynamic random access memory (DRAM), for example, is used as a main memory of a processor. Further, in the conventional information processing device, a secondary memory (storage) device is used in combination with the volatile memory.
In the conventional information processing device, the contents of the main memory are lost if the power source thereof is turned off. Therefore, in the conventional information processing device, the boot operation of a system is required at each boot time, it is required to move a program or data from the secondary memory device to the main memory for program starting or data reading and it takes a long time for execution.
Further, in the conventional information processing device, the contents of the main memory cannot be maintained if the power source thereof is turned off. Therefore, when the conventional information processing device is not correctly shut down, there occurs a possibility that data, a system or program will be destroyed.
In a Document 1 (Jpn. Pat. Appln. KOKAI Publication No. H7-146820), a technique for utilizing a flash memory as a main memory of an information processing device is disclosed. In the Document 1, the flash memory is connected to a memory bus of a system via a cache memory that is a volatile memory. In the cache memory, an address array that records information such as an access history or an address of data stored in the cache memory is provided. A controller refers to an address of an access destination, and supplies data of the cache memory or flash memory to the memory bus or stores data of the memory bus.
A document 2 (Jpn. Pat. Appln. KOKAI Publication No. 2001-266580) discloses an invention enable different kind of semiconductor memory devices to be connected to a common bus.
The semiconductor memory device disclosed in the document 2 includes a random access memory chip and a package having the random access memory chip. The package comprises a plurality of pins electrically connecting the random access memory chip to an external device. The pins provide a memory function in common to a random access memory and an electrically erasable and programmable non-volatile semiconductor memory. The pins are arrayed according to the corresponding pin position of the non-volatile semiconductor memory.